AEG SB4 series User Manual Page 164
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Programming in Dolog B
152
A.7.2 Delay Time of the END Block (or Program End in Dolog AKF)
In each VList cycle the end block is processed once. The delay time of the END block
is derived from the basic time plus the times for the:
PEAB I/O modules
remote I/O modules
t
End
= basic time + t
PEAB
+t
BB1
+t
BB2
+t
BB3
+t
BB4
where
t
PEAB
= number of the 16 bit PEAB I/O groups x 0.145 ms
t
BB1
= number of the DEA 10x6 modules on Modnet 1/SFB x, the corresponding
delay time see Table 38
t
BB2
= number of the DEP/DAP 112 modules on a Modnet 1/SFB x, the correspon-
ding delay time see Table 38
t
BB3
= number of the DAP 102 modules on a Modnet 1/SFB x, the corresponding
delay time see Table 38
t
BB4
= number of the DEA-H1/K1 modules on a Modnet 1/SFB x, the corresponding
delay time see Table 38
The following times are applicable:
Basic time: 4.032 ms
PEAB I/O (per 16 bit) 0.145 ms
remote I/O: see Table 38
Table 38 Delay Time of Remote I/O
Delay Times in ms for 62.5 KBd 375 KBd 2 MBd
DEA-H1/K1 10.0 2.5 1,7
DEA 1x6 9.0 2.5 1.9
DEP/DAP 112 1.0 0.5 0.3
DAP 102 2.0 0.8 0.6
Note The cycle time is reduced when several BIKs are used for the planned number
of I/O modules. If more than one BIK is available, the individual BIK are directed one
after the other. The I/O are then obtained almost parallel. As the directing time for
62.5 KBd and 375 KBd is much shorter than the transmission time of the message, the
delay time is reduced. A decisive factor for the entire cycle time is then primarily the
Modnet 1/SFB with the most I/O modules.
In the 2 MBd the delay time gains through the use of several BIK is not decisive.
- Terminology 3
- Objectives 3
- Arrangement of This Guide 4
- Related Documents 5
- Table of Contents 12
- Chapter 1 13
- 1.1 Introduction 14
- 1.2 Compatibility 14
- 1.3 General Mode of Operation 15
- 1.3.2 Central Processing Unit 16
- 1.3.3 I/O Modules 16
- 1.3.4 Busses 17
- 1.4 Structure 18
- DEA 106, DEA 116 or DEA 156 20
- 1.4.3 Configuration Limits 22
- 1.5 Recommended Peripherals 23
- 1.6 Programming 24
- 1.7 Networking 28
- A500 (Master) 29
- 1.8 Tesy 31
- 1.10 Module Survey 33
- Chapter 2 37
- Operating 37
- 2.1 Indicating Elements 38
- 2.2.1 Switches 40
- 2.2.2 Contact Sockets 40
- 2.2.3 Push Buttons 40
- 7) E-No. 424 142 148 41
- Chapter 3 45
- DEA 106 or DEA 156 52
- DEA 106/DEA 116 60
- DTA 102/DTA 112 60
- DTA 103/DTA 113 60
- Slot references 60
- DTA 028 primary subrack 61
- in stages of 62
- 32 for 1st DKV 62
- 64 for 2nd DKV, ....) 62
- and are to be set in each 62
- 12345678910111213141516 63
- Table 20 Types of Addressing 64
- Rear Connection 70
- 3.2.2 Port Diagram of the U 70
- =24VDC/L= 77
- 3.5 PEAB Monitoring 84
- 3.6 Start-Up Characteristics 86
- 3.7 Installation 88
- 3.7.3 Discharge Measures 92
- F Automatic circuit breaker 95
- I/O module 95
- 3.7.4 Connecting Peripheries 98
- 3.8 Addressing the Memory 100
- 3.8.6 Special Marker Area 104
- 3.9.3 Initial Start-Up 109
- 3.10 Further Information 110
- 3.10.2 PEAB Time Error 111
- Configuration 114
- 3.11.3 Program Archiving 116
- Chapter 4 117
- Specifications 117
- 4.2 Interfaces 119
- 4.3 Processor 124
- 4.4 Processing Times 125
- 4.5 Memories 125
- 4.6 Physical Characteristics 126
- 4.7 Environmental Data 128
- Chapter 5 131
- Earthing and EMC-Measures 131
- 5.1.3 Functional Earthing 133
- 5.2 EMC Measures 136
- Correct: 137
- Actuators 139
- 5.3 Interference Suppression 140
- Appendix A 143
- Programming in Dolog B 143
- Connection List) 144
- A.1.4 Interrupt VList 148
- A.2 Program Input 149
- A.4.1 Online Parameters 151
- A.4.2 Online Programming 152
- A.4.3 Online Testing 153
- A.4.4 Online Documenting 153
- A.6 ListofDologBBlocks 157
- A.7 Cycle Time 163
- Dolog AKF 166
- Appendix B 177
- Module Descriptions 177
- ALU 011, ALU 012, ALU 021 179
- Central Processing Unit 179
- Module Description 179
- 1 General 180
- 1.5 Variants 184
- 1.6 Physical Characteristics 185
- 1.7 Mode of functioning 186
- 3 Configuration 188
- 3.4 Start-up characteristics 192
- 3.6 Settig status bits 196
- 3.7 Program abortion 197
- 3.8 RS 232C Interface (V.24) 197
- 3.9 Hardware clock 198
- 3.11 Process interface 199
- 3.12 Documentation 199
- 3.13 Software notes 200
- 4 Specifications 201
- ALU 061, ALU 071 203
- Modicon A500 204
- 2 Operation / Presentation 206
- 3.2 Memory Functions 210
- MME 001 / MME 002 212
- 3.4 Setting Status Bits 216
- 3.6 Program Abortion 217
- 3.7 Ports and Interfaces 218
- 3.9 Software Notes 219
- 3.10 Dokumentation 220
- ALU 150214 226
- 2 Operation and Display 228
- 3.1 Basic Software 229
- 3.2 Baudrate 230
- Modnet 1/SFB Interface for 237
- Central Processing Units 237
- BIK 151190 238
- 3.3 Addressing 242
- 3.5 Documentation 244
- Coprocessor 247
- COP 82200 248
- 3.2 Data Back-Up 251
- 3.3 Address Area Setting 251
- 3.5 Status Bits 252
- 3.6 Serial Interface 252
- 3.7 Using an “Active PMB” 252
- PEAB Network 255
- DKV 023208 256
- C64MC64M 256
- 3.3 Documentation 259
- 24 VDC Power Supply 261
- DNO 028214 262
- 3.3 Backup Time Extension 265
- 3.4 Connector Pin Assignment 266
- 220 VAC Power Supply 269
- DNP 023222 270
- 3.4 Slot Coding 273
- 3.5 Backup Time Extension 274
- 3.6 Connector Pin Assignment 274
- 3.7 Documentation 274
- DNP 023-1, DNP 023-2 276
- Power Supply 276
- Frontrippen 277
- Berührung mit 277
- 3.3 Wiring in the Subracks 280
- 3.5 Voltage Control for +5 V 281
- 3.6 Backup Time Extension 281
- 3.8 Connector Pin Assigment 283
- DNP 023-3, DNP 023-4 286
- 3.3 Wiring in the Subrack 290
- 3.8 Documentation 292
- 3.9 Connector Pin Assignment 293
- DNP 028250 297
- H11M C64M 297
- 3.3 Graphical Symbols 300
- 3.4 Documentation 300
- DNP 028DNP 028DNP 028 301
- Leading power supply 301
- 3.5 Equipping the PMB Area 307
- 3.6 Equipping the PEAB Area 307
- 3.8 RAK Chain 308
- 3.9 Ventilation 308
- 3.10 EMC Measures 308
- 3.11 Documentation 308
- 3.12 Dimensions 309
- DTA 27.1 312
- 3.2 Supply Ports 315
- 3.3 Fault Message 315
- 3.4 Supply Wiring 317
- 3.5 Supply Monitoring 317
- DNP 023-x 317
- (see Figure 145) 318
- 3.7 PEAB Coupling 319
- 3.9 Backing Up the Mains 319
- P: PEAB port 320
- 3.12 Modnet 1/N Port 321
- 3.13 Using the B500-2 321
- 3.5 Equipment of the PMB Area 327
- 3.10 Port of the Periphery 328
- 3.11 EMC Measures 329
- 3.13 Dimensions 331
- 1.2 Mode of Functioning 336
- 3.3 Z Screw, Z Jumper 339
- 3.2 Supply Wiring 348
- 3.3 Supply Monitoring 348
- 3.4 Mains Backup 348
- 3.5 Occupation of the Subrack 348
- 3.7 Error Message 350
- 3.10 B500-2 Use 351
- Mounting Flange Use 353
- 3.14 Documentation 355
- Modnet 1N Interface 358
- KOS 152312 359
- 3.2 Addressing 363
- 3.3 Settings for Networking 365
- 3.4 Settings for Tesy 367
- 3.5 Current Loop Operation 368
- 3.7 Connection Cable 369
- 3.8 Ventilation 369
- Communication Processor 372
- KOS 882326 373
- 3.3 Programming 377
- 3.4 Transmission Rate 377
- 3.6 Ventilation 377
- Air Guide 380
- Arithmetic Processor 384
- 2 Operating and Display 386
- 3.1 Mounting the MAT 827 387
- 3.2 Documentation 387
- Cabinet Connection Unit 390
- 3.2 Dimension Specifications 393
- SC 8128 / SC 8256 396
- Memory Module (RAM) 396
- SC 8128 / SC 8256350 397
- 3.1 Coding 399
- 3.2 Write Disable 399
- Memory Module (EPROM) 402
- SF 8512356 403
- 3.2 Coding the Address Areas 405
- 3.3 Ventilation 406
- Monitoring Module 408
- UKA 024362 409
- 3.4 Graphical Symbols 412
- 3.5 Plug-In Check 412
- 3.6 PEAB Monitoring 412
- 3.10 Documentation 417
- 3.11 Connector Pin Assignment 418
- 24 VDC o—o o—o o—o 420
- 48 VDC o o o—o o o 420
- 60 VDC o o o o o o 420
- UVL 841, UVL 842 424
- Interface Converter 424
- 3.1 Functional Jumpers 427
- 3.2 Interface Supply 427
- 3.3 Cables 427
- 3.5 Graphical Symbols 429
- 3.6 Documentation 429
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